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CS8954 general purpose 8051 mcu 64k flash type with isp myson century, inc. taiwan: no. 2, industry east rd. iii, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 sales@myson.com.tw www.myson.com.tw rev. 0.4 april 2003 page 1 of 21 usa: 4020 moorpark avenue suite 115 san jose, ca, 95117 tel: 408-243-8388 fax: 408-243-3188 general descriptions the CS8954 micro-controller is an 8051 cpu core embedded device especially tailored for consumer and/or general purpose applications. it includes an 8051 cpu core, 768-byte sram, 4 channels of 6-bit adc, 6 channels of pwm dac, and a 64k-byte internal program flash-rom memory in 40-pin pdip, 44-pin plcc or pqfp package. features 8051 core, 12mhz operating frequency with single/double cpu clock option 0.35um process 3.3v power supply 768-byte ram 64k-byte program flash memory maximum 6 channels of pwm dac watchdog timer with programmable interval single/double frequency clock output hardware in system programming (isp) without boot code two external interrupts maximum 4 channels of 6-bit adc flash-rom code protection selection 40-pin pdip, 44-pin plcc or pqfp package block diagram auxram p0.0-7 p2.0-3 rd wr ale int1 8051 core p1.0-7 p3.0-2 p3.4 rst x1 x2 adc a d0-3 pwm dac da0-5 xfr p0.0-7 p2.0-7 rd wr a le int1 p6.0-7 p5.0-6 aux i/o p7.6-7 cko
CS8954 page 2 of 21 pin connection CS8954n 40-pin pdip 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vcc p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 nc nc nc p6.7 p6.6 p6.5 p6.4 p6.3/ad3 p6.2/ad2 p6.1ad1 p6.0/ad0 p5.0/da0 p5.1/da1 p5.2/da2 p5.3/da3 p5.4/da4 p5.5/da5 p5.6 p5.7 rst p3.0/rxd0 p3.1/txd0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p7.6/clk0 p7.7 x2 x1 vss
CS8954 page 3 of 21 CS8954v 44-pin plcc p1.4 p1.5 p1.6 p1.7 nc nc nc nc p6.7 p6.6/clko p6.5 p5.5/da5 p5.6 p5.7 rst rxd0/p3.0 nc txd0/p3.1 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p5.4/da4 p5.3/da3 p5.2/da2 p5.1/da1 p5.0/da0 nc vcc p1.0 p1.1 p1.2 p1.3 p7.6/clk0 p7.7 x2 x1 gnd nc p6.0/ad0 p6.1/ad1 p6.2/ad2 p6.3/ad3 p6.4 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40
CS8954 page 4 of 21 CS8954f 44-pin pqfp p1.4 p1.5 p1.6 p1.7 nc nc nc nc p6.7 p6.6/clko p6.5 p5.5/da5 p5.6 p5.7 rst rxd0/p3.0 nc txd0/p3.1 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p5.4/da4 p5.3/da3 p5.2/da2 p5.1/da1 p5.0/da0 nc vcc p1.0 p1.1 p1.2 p1.3 p7.6/clk0 p7.7 x2 x1 gnd nc p6.0/ad0 p6.1/ad1 p6.2/ad2 p6.3/ad3 p6.4 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
CS8954 page 5 of 21 pin configuration a ?cmos output pin? means it can sink and drive at least 4ma current. it is not recommended to use such pin as input function. a ?open drain pin? means it can sink at least 4ma current. it can be used as input or output function and needs an external pull up resistor. a ?8051 standard pin? is a pseudo open drain pin. it can sink at least 4ma current when output is at low level, and drives at least 4ma current for 160ns when output transits from low to high, then keeps driving at 100ua to maintain the pin at high level. it can be used as input or output function. it needs an external pull up resistor when driving heavy load device. there is an internal-pull down resistance on each cmos pad and an internal pull-down resistance on each input pad. it is recommended to add a pull high resistance on each open drain pin. 8051 standard pin 4ma 4ma output data pin cmos output pin open drain pin 2 osc period delay 4ma 10ua output data 120ua pin 4ma input data no current 4ma output data pin input data
CS8954 page 6 of 21 pin description name pin no. i/o description nc 1 - no connection p5.0/da0 2 i/o general purpose i/o (open drain) p5.1/da1 3 i/o general purpose i/o (open drain) p5.2/da2 4 i/o general purpose i/o (open drain) p5.3/da3 5 i/o general purpose i/o (open drain) p5.4/da4 6 i/o general purpose i/o (open drain) p5.5/da5 7 i/o general purpose i/o (open drain) p5.6 8 i/o general purpose i/o p5.7 9 i/o general purpose i/o rst 10 i high active reset p3.0/rxd0 11 i/o serial port 0 input nc 12 - no connection p3.1/txd0 13 i/o serial port 0 output p3.2/int0 14 i/o general purpose i/o /external interrupt(standard 8051) p3.3/int1 15 i/o general purpose i/o /external interrupt(standard 8051) p3.4/t0 16 i/o general purpose i/o (standard 8051) p3.5/t1 17 i/o general purpose i/o (standard 8051) p7.6/clko 18 i/o general purpose i/o /clock out (cmos) p7.7 19 i/o general purpose i/o (cmos) x2 20 o crystal out x1 21 i crystal in vss 22 - ground nc 23 - no connection p6.0/ad0 24 i/o general purpose i/o (cmos) /6-bit adc channel 0 input p6.1/ad1 25 i/o general purpose i/o (cmos) /6-bit adc channel 1 input p6.2/ad2 26 i/o general purpose i/o (cmos) /6-bit adc channel 2 input p6.3/ad3 27 i/o general purpose i/o (cmos) /6-bit adc channel 3 input p6.4 28 i/o general purpose i/o (cmos) p6.5 29 i/o general purpose i/o (cmos) p6.6 30 i/o general purpose i/o (cmos) p6.7 31 i/o general purpose i/o (cmos) nc 32 - no connection nc 23 - no connection nc 23 - no connection nc 35 i/o no connection p1.7 36 i/o general purpose i/o (standard 8051) p1.6 37 i/o general purpose i/o (standard 8051) p1.5 38 i/o general purpose i/o (standard 8051)
CS8954 page 7 of 21 p1.4 39 i/o general purpose i/o (standard 8051) p1.3 40 i/o general purpose i/o (standard 8051) p1.2 41 i/o general purpose i/o (standard 8051) p1.1 42 i/o general purpose i/o (standard 8051) p1.0 43 i/o general purpose i/o (standard 8051) vcc 44 - 3.3v power
CS8954 page 8 of 21 functional descriptions 8051 cpu core the cpu core of CS8954 is compatible with the industry standard 8051, which includes 256 bytes ram, special function registers (sfr), two timers, five interrupt sources and a serial interface. the cpu core fetches its program code from the 64k bytes flash memory in CS8954. it uses port0 and port2 to access the ?external special function register? (xfr) and external auxiliary ram (auxram). the cpu core can run at single/double rate when fclke is set. once one of the bits is set, the cpu runs as if a 24mhz x?tal is applied on CS8954, but the peripherals (ddc, for example) still run at the original frequency. note: all registers listed in this document reside in 8051?s external ram area (xfr). for internal ram memory map, please refer to 8051 spec.. memory allocation i) internal special function registers (sfr) the sfr is a group of registers that are the same as standard 8051. ii) internal ram there are total 256 bytes internal ram in CS8954, the same as standard 8052. iii) external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area f00h ? fffh. these registers are used for special functions. programs can use "movx" instruction to access these registers. iv) auxiliary ram (auxram) there are total 512 bytes auxiliary ram allocated in the 8051 external ram area 800h - 8ffh and e00h - effh. programs can use "movx" instruction to access the auxram. 800h 8ffh e00h effh auxram accessible by indirect external ram addressing (using movx instruction) auxram accessible by indirect external ram addressing (using movx instruction 00h 7fh 80h ffh internal ram accessible by indirect addressing only (using mov a,@ri instruction) internal ram accessible by direct and indirect addressing sfr accessible by direct addressing f00h fffh xfr accessible by indirect external ram addressing (using movx instruction)
CS8954 page 9 of 21 chip configuration the chip configuration registers define configuration of the chip and function of the pins. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod f50h(w) ad0e padmod f51h(w) p55e p54e p53e p52e p51e p50e padmod f52h(w) rev0 rev0 padmod f53h(w) p57oe p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke dclk ip77e padmod f5eh(w) padmod f5fh(w) p77oe p76oe padmod (w) : pad mode control registers. (all are "0" in chip reset. the registers named as ?rev0? are reserved for testing, all of them should be written ?0? after reset) ad0e = 1 pin ?p6.0/ad0? is ad0. = 0 pin ?p6.0/ad0? is p6.0. p55e = 1 pin ?da5/p5.5? is p5.5. = 0 pin ?da5/p5.5? is da5. p54e = 1 pin ?da4/p5.4? is p5.4. = 0 pin ?da4/p5.4? is da4. p53e = 1 pin ?da3/p5.3? is p5.3. = 0 pin ?da3/p5.3? is da3. p52e = 1 pin ?da2/p5.2? is p5.2. = 0 pin ?da2/p5.2? is da2. p51e = 1 pin ?da1/p5.1? is p5.1. = 0 pin ?da1/p5.1? is da1. p50e = 1 pin ?da0/p5.0? is p5.0. = 0 pin ?da0/p5.0? is da0. rev0 = 0 these 2 bit must be written to 0 after chip reset p57oe = 1 p5.7 is output pin. = 0 p5.7 is input pin. p56oe = 1 p5.6 is output pin. = 0 p5.6 is input pin. p55oe = 1 p5.5 is output pin. = 0 p5.5 is input pin. p54oe = 1 p5.4 is output pin. = 0 p5.4 is input pin. p53oe = 1 p5.3 is output pin. = 0 p5.3 is input pin. p52oe = 1 p5.2 is output pin.
CS8954 page 10 of 21 = 0 p5.2 is input pin. p51oe = 1 p5.1 is output pin. = 0 p5.1 is input pin. p50oe = 1 p5.0 is output pin. = 0 p5.0 is input pin. p67oe = 1 p6.7 is output pin. = 0 p6.7 is input pin. p66oe = 1 p6.6 is output pin. = 0 p6.6 is input pin. p65oe = 1 p6.5 is output pin. = 0 p6.5 is input pin. p64oe = 1 p6.4 is output pin. = 0 p6.4 is input pin. p63oe = 1 p6.3 is output pin. = 0 p6.3 is input pin. p62oe = 1 p6.2 is output pin. = 0 p6.2 is input pin. p61oe = 1 p6.1 is output pin. = 0 p6.1 is input pin. p60oe = 1 p6.0 is output pin. = 0 p6.0 is input pin. cop17 = 1 pin ?p1.7? is cmos output. = 0 pin ?p1.7? is 8051 standard i/o. cop16 = 1 pin ?p1.6? is cmos output. = 0 pin ?p1.6? is 8051 standard i/o. cop15 = 1 pin ?p1.5? is cmos output. = 0 pin ?p1.5? is 8051 standard i/o. cop14 = 1 pin ?p1.4? is cmos output. = 0 pin ?p1.4? is 8051 standard i/o. cop13 = 1 pin ?p1.3? is cmos output. = 0 pin ?p1.3? is 8051 standard i/o. cop12 = 1 pin ?p1.2? is cmos output. = 0 pin ?p1.2? is 8051 standard i/o. cop11 = 1 pin ?p1.1? is cmos output. = 0 pin ?p1.1? is 8051 standard i/o. cop10 = 1 pin ?p1.0? is cmos output. = 0 pin ?p1.0? is 8051 standard i/o. p77oe = 1 p7.7 is output pin. = 0 p7.7 is input pin. p76oe = 1 p7.6 is output pin. = 0 p7.6 is input pin. ip77e = 1 pin ?p7.7 is p7.7 if ip76e = 1 in ice mode. = 0 reserved.
CS8954 page 11 of 21 option (w) : chip option configuration (all are "0" in chip reset). pwmf = 1 selects 94khz pwm frequency. = 0 selects 47khz pwm frequency. div253 = 1 pwm pulse width is 253-step resolution. = 0 pwm pulse width is 256-step resolution. fclke = 1 cpu is running at double rate = 0 cpu is running at normal rate dclk = 1 cko outputs double frequency system clock. = 0 cko outputs single frequency system clock. i/o ports i) port1 port1 is a group of pseudo open drain pins or cmos output pins. it can be used as general purpose i/o. behavior of port1 is the same as standard 8051. ii) p3.0-2, p3.4 if these pins are not set as iic pins, port3 can be used as general purpose i/o, interrupt, uart and timer pins. behavior of port3 is the same as standard 8051. iii) port5, port6 and port7 port5, port6 and port7 are used as general purpose i/o. s/w needs to set the corresponding p5(n)oe and p6(n)oe to define whether these pins are input or output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port5 f37h(r/w) p57 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 port7 f76h(r/w) p76 port7 f77h(r/w) p77
CS8954 page 12 of 21 port5 (r/w) : port 5 data input/output value. port6 (r/w) : port 6 data input/output value. pwm dac each output pulse width of pwm dac converter is controlled by an 8-bit register in xfr. the frequency of pwm clock is 47khz or 94khz, selected by pwmf. and the total duty cycle step of these dac outputs is 253 or 256, selected by div253. if div253=1, writing fdh/feh/ffh to dac register generates stable high output. if div253=0, the output pulses low at least once even if the dac register's content is ffh. writing 00h to dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 da0-5 (r/w) : the output pulse width control for da0-5. * all of pwm dac converters are centered with value 80h after power on. a/d converter the CS8954 is equipped with 4 vdd range 6-bit a/d converters. the adc conversion range is from vss to vdd, s/w can select the current convert channel by setting the sadc3 - sadc0 bit. the refresh rate for the adc is osc freq./1536 (128us for 12mhz x'tal). the adc compares the input pin voltage with internal vdd*n/64 voltage (where n = 0 - 63). the adc output value is n when pin voltage is greater than vdd*n/64 and smaller than vdd*(n+1)/64. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0 wdt (w) : watchdog timer control register. wen = 1 enables watchdog timer. wclr = 1 clears watchdog timer. wdt2: wdt0 = 0 overflow interval = 8 x 0.25 sec. = 1 overflow interval = 1 x 0.25 sec. = 2 overflow interval = 2 x 0.25 sec. = 3 overflow interval = 3 x 0.25 sec. = 4 overflow interval = 4 x 0.25 sec. = 5 overflow interval = 5 x 0.25 sec. = 6 overflow interval = 6 x 0.25 sec. = 7 overflow interval = 7 x 0.25 sec.
CS8954 page 13 of 21 adc (w) : adc control. enadc = 1 enables adc. sadc0 = 1 selects adc0 pin input. sadc1 = 1 selects adc1 pin input. sadc2 = 1 selects adc2 pin input. sadc3 = 1 selects adc3 pin input. adc (r) : adc convert result. in system programming function (isp) the flash memory can be programmed by a specific writer in parallel mode, or by iic host in serial mode while the system is working. the features of isp are outlined as below: 1. single 3.3v power supply for program/erase/verify. 2. block erase: 1024 bytes for program code, 10ms 3. whole flash erase (blank): 10ms 4. byte/word programming cycle time: 60us per byte 5. read access time: 50ns 6. only one two-pin iic bus (shared with ddc2) is needed for isp in user/factory mode. 7. iic bus clock rates up to 140khz. 8. whole 64k-byte flash programming within 6 sec.(it depends on the external iic speed) 9. crc check provides 100% coverage for all single/double bit errors. there are two methods to enter the isp mode which are described as below: method 1). the valid isp slave address and compared data are transmitted method 2). write 93h to isp enable register (ispen) reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ispslv f0bh(w) isp slave address ispen f0ch(w) write 93h to enable isp mode ispslv (w) : isp slave iic's address. bit7-2 : isp slave iic's address to which the isp block should respond. the default value is 100101. ispen (w) : write 93h to enable isp mode for isp enable method 2. memory map of xfr address f00h to f0ah are all reserved for testing, user should not change their values or just keep them all 0 after reset. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rev f00h (w) rev rev rev rev rev rev rev rev rev f01h (w) rev rev rev rev rev rev rev rev rev f02h (w) rev rev rev rev rev rev rev rev rev f03h (w) rev rev rev rev rev rev rev rev rev f04h (w) rev rev rev rev rev rev rev rev
CS8954 page 14 of 21 rev f06h (w) rev rev rev rev rev rev rev rev rev f07h (w) rev rev rev rev rev rev rev rev rev f08h (w) rev rev rev rev rev rev rev rev rev f09h (w) rev rev rev rev rev rev rev rev rev f0ah (w) rev rev rev rev rev rev rev rev ispslv f0bh(w) isp slave address ispen f0ch(w) write 93h to enable isp mode ispcmp1 f0dh(w) isp compared data 1 [7:0] ispcmp2 f0eh(w) isp compared data 2 [7:0] ispcmp3 f0fh(w) isp compared data 3 [7:0] adc f10h (w) enadc sadc3 sadc2 sadc1 sadc0 adc f10h (r) adc convert result wdt f18h (w) wen wclr wdt2 wdt1 wdt0 da0 f20h(r/w) pulse width of pwm dac 0 da1 f21h(r/w) pulse width of pwm dac 1 da2 f22h(r/w) pulse width of pwm dac 2 da3 f23h(r/w) pulse width of pwm dac 3 da4 f24h(r/w) pulse width of pwm dac 4 da5 f25h(r/w) pulse width of pwm dac 5 port5 f30h(r/w) p50 port5 f31h(r/w) p51 port5 f32h(r/w) p52 port5 f33h(r/w) p53 port5 f34h(r/w) p54 port5 f35h(r/w) p55 port5 f36h(r/w) p56 port6 f38h(r/w) p60 port6 f39h(r/w) p61 port6 f3ah(r/w) p62 port6 f3bh(r/w) p63 port6 f3ch(r/w) p64 port6 f3dh(r/w) p65 port6 f3eh(r/w) p66 port6 f3fh(r/w) p67 padmod f50h(w) da13e da12e da11e da10e ad3e ad2e ad1e ad0e padmod f51h(w) p57e p56e p55e p54e p53e p52e p51e p50e padmod f52h(w) rev0 rev0 padmod f53h(w) p57oe p56oe p55oe p54oe p53oe p52oe p51oe p50oe padmod f54h(w) p67oe p66oe p65oe p64oe p63oe p62oe p61oe p60oe padmod f55h(w) cop17 cop16 cop15 cop14 cop13 cop12 cop11 cop10 option f56h(w) pwmf div253 fclke dclk ip77e
CS8954 page 15 of 21 padmod f5eh(w) padmod f5fh(w) p77oe p76oe port7 f76h(r/w) p76 port7 f77h(r/w) p77 etctr f88h (w) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 f88h (r) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 etmod f89h (w) dcen f89h (r) dcen f8ah (w) thet f8ah (r) thet f8bh (w) tlet f8bh (r) tlet f8ch (w) rcapeth f8ch (r) rcapeth f8dh (w) tcapetl f8dh (r) tcapetl eint1pen f8eh (w) eeint1 ete tstp1
CS8954 page 16 of 21 electrical parameters absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +3.6 v maximum input voltage (hsync, vsync & open-drain pins) vin1 -0.3 to 3.3+0.3 v maximum input voltage (other pins) vin2 -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 c maximum storage temperature tstg -25 to +125 c allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol condition min. max. unit supply voltage vdd 3.3v applications 3.0 3.6 v input "h" voltage vih 3.3v applications 0.6 x vdd vdd +0.3 v input "l" voltage vil 3.3v applications -0.3 0.3 x vdd v operating freq. fopg - 15 mhz dc characteristics at: ta=0 to 70 o c, vdd=3.3v, vss=0v name symbol condition min. typ. max. unit output "h" voltage, open drain pin voh1 vdd=3.3v, ioh=0ua 2.65 v output "h" voltage, 8051 i/o port pin voh2 vdd=3.3v, ioh=- 50ua 2.65 v output "h" voltage, cmos output voh3 vdd=3.3v, ioh=- 4ma 2.65 v output "l" voltage vol iol=5ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=3.3v 150 250 kohm pin capacitance cio 15 pf
CS8954 page 17 of 21 ac characteristics at: ta=0 to 70 o c, vdd=3.3v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 12 mhz pwm dac frequency fda fxtal=12mhz 46.875 94.86 khz hs input pulse width thipw fxtal=12mhz 0.3 7.5 s vs input pulse width tvipw fxtal=12mhz 3 s hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=12mhz 8 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 s test mode condition in normal application, users should avoid the CS8954 entering its test mode or writer mode, outlined as follows: adding pull-up resistor to hscl1/hsda1/hscl2/hsda2 pins is recommended. test mode: reset's falling edge & p3.0=0 & p3.1=0 & p5.6 = 0
CS8954 page 18 of 21 package dimension 40-pin pdip dimension in millimeters dimension in inches symbol min nom max min nom max a1 1.65 1.78 1.91 0.065 0.070 0.075 a2 3.81 3.94 4.06 0.150 0.155 0.160 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 1.22 1.27 1.37 0.048 0.050 0.054 c 0.20 0.25 0.36 0.008 0.010 0.014 d - 52.18 52.58 - 2.055 2.070 e1 13.59 13.72 13.84 0.535 0.540 0.545 e2 14.99 15.24 15.49 0.590 0.600 0.610 e3 16.00 16.51 17.02 0.630 0.650 0.670 e 2.29 2.54 2.79 0.090 0.100 0.110 l1 3.05 3.30 3.56 0.120 0.130 0.140 l2 0.254 - - 0.010 - - 0o 7.5o 15o 0o 7.5o 15o
CS8954 page 19 of 21 44-pin plcc dimension in millimeters dimension in inches symbol min nom max min nom max a - - 4.70 - - 0.185 a1 0.51 - - 0.020 - - a2 3.70 3.80 3.90 0.145 0.150 0.155 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 0.65 0.70 0.80 0.026 0.028 0.032 c 0.18 0.25 0.33 0.007 0.010 0.013 d 16.46 16.60 16.71 0.648 0.653 0.658 e 16.46 16.60 16.71 0.648 0.653 0.658 e 1.27 (typ) 0.050 (typ) gd 15.00 15.50 16.00 0.590 0.610 0.630 ge 15.00 15.50 16.00 0.590 0.610 0.630 hd 17.30 17.50 17.80 0.680 0.690 0.700 he 17.30 17.50 17.80 0.680 0.690 0.700 l 2.29 2.54 2.80 0.090 0.100 0.110 0o - 10o 0o - 10o
CS8954 page 20 of 21 44-pin pqfp dimension in millimeters dimension in inches symbol min nom max min nom max a - - 2.70 - - 0.105 a1 0.25 0.30 0.35 0.010 0.012 0.014 a2 1.90 2.00 2.20 0.075 0.079 0.087 b 0.3 (typ) 0.012 (typ) c 0.10 0.15 0.20 0.004 0.006 0.008 d 13.00 13.20 13.40 0.510 0.520 0.530 d1 9.90 10.00 10.10 0.390 0.040 0.041 e 13.00 13.20 13.40 0.510 0.520 0.530 e1 9.90 10.00 10.10 0.390 0.040 0.041 e 0.80 (typ) 0.030 (typ) l 0.73 0.88 0.93 0.029 0.035 0.037 l1 - 1.60 - - 0.063 - 0o - 7o 0o - 7o
CS8954 page 21 of 21 ordering information standard configurations: prefix part type package type cs 8954n 8954v 8954f n: pdip v: plcc f: pqfp

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	To Download CS8954 Datasheet File
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